The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to an impedance control system for a center tapped termination bus.
Data buffers are used on a variety of integrated circuit devices to receive and drive data values between one device and another circuit coupled with to it. These data buffers are commonly connected to data buses that connect the output of a buffer to a receiving buffer of another device. Since a number of output buffers are often coupled to an individual bus, interface protocols have been developed to regulate signaling. Different aspects of a bus standard specify the impedance of a buffer when the buffer is driving a signal, the terminating impedance of a buffer when the buffer is not driving a signal, and signal voltage swing.
Double data rate (DDR) dynamic random access memory (DRAM) systems use a center-tapped termination (CTT) to control bus reflections. The buffers that drive the DDR bus are usually strong buffers with a series resistor to compensate the buffer to a target impedance that gives a target swing on the bus. An example of such system is shown in FIG. 1.
FIG. 1 illustrates an example of a prior art system 100 having a DDR bus 106. In this example, there are three agents (memory controller 102, DDR DRAM 114, DDR DRAM 118) coupled to the DDR bus 106. These agents 102, 114, 116 can be a driver or a receiver on the bus 106 at different times. The buffer of memory controller 102 is coupled to the bus 106 through a series resistance Rs 104. This resistance can be internal to the buffer itself and is present to ensure good signal integrity on the bus 106. Similarly, the buffers of DDR DRAMs 114, 118 are also coupled to the bus 106 through Rs 112 and 116, respectively. The bus 106 of this example includes a pair of impedances RT1 108 and RT2 110, which are termination resistances to help control signaling quality on the bus 106. Note that the termination resistances RT1 108 and RT2 110 can be replaced with a single resistor with a value equal to RT1 108 and RT2 110 in parallel and connected to a different termination voltage equal to VTERM(RT1/(RT1+RT2)), the Thevenin voltage.
The series resistors Rs 104, 112, 116 plus the buffer impedance are set to give good signal integrity on the bus 106. The series resistor value may be different for the memory controller 102 and the DDR DRAM 114, 118. The CTT resistors set the reference level for the bus 106 around which the signal swing is set. The signal swing is determined by the ratio of buffer impedance plus Rs to the Thevenin resistance of the CTT (RT1 108 in parallel to RT2 110).
Some drivers have been developed that integrate the resistor Rs into the buffer driver. But some semiconductor processes do not have resistances with sufficiently good accuracy and temperature coefficient that can produce a buffer that will meet the DDR specifications. However, an impedance compensation capability is available that can be adapted to facilitate this need. A standard prior art synchronous, impedance compensated buffer is shown in FIG. 2.
FIG. 2 is a prior art schematic diagram of a programmable strength buffer 200. The programmable strength buffer 200 of this example receives a number of input signals: PENB[0::x] 202, DATA 204, OE 206, CLOCK 208, and NEN[0::x] 210. PENB[0::x] 202 is a number of trim signals used to adjust the strength of adjustable P type transistor device P1 230. Similarly, NEN[0::x] 210 is a number of trim signals for adjusting the strength of adjustable N type transistor device N1 232.
The pull-up P1 230 and pull-down N1 232 transistors are made from multiple legs that can be enabled or disabled by the strength control bits PENB[0::x] 202 and NEN[0::x] 210, respectively. The OR gates 222 and AND gates 224 are only illustrative in purpose. The necessary logic varies depending on the particular implementation.
DATA input 204 is coupled to data latches 218, 220 through logic 212, 216 controlled with output enable signal OE 206. The outputs of data latches 218, 220 are coupled to logic 222, 224. Data latches 218, 220 latch and output DATA 204 to logic 222, 224 when OE 206 and CLOCK 208 are activated. The source terminal of P1 230 is connected to a VCC supply voltage and the gate terminals are connected to the outputs of logic 222. The source terminal of N1 232 is connected to a ground potential and the gate terminals are connected to the outputs of logic 224. The drain terminals of P1 230 and N1 232 are connected together with a first terminal of resistor Rs 234. Rs 234 also serves to linearize the voltage-current output characteristics of the buffer 200 as well as help set the proper buffer impedance. The second terminal of Rs 234 is connected to pad 236.